The present invention relates to an image processing method and apparatus thereof and, more particularly to an image processing method and apparatus capable of decoding the coded image data obtained in such a way that image data is divided into a plurality of stripes, each of which is then encoded into a plurality of frames having different resolution levels of this coded image data.
FIG. 1 is a diagram illustrating the structure of the image data when stripe hierarchical processing is performed using the JBIG (Joint Bi-level Image Coding Experts Group) method. The image data in each stripe is arranged from the left to the right in the sequence from a low resolution to high resolution. For example, the stripe having stripe No. 0 includes the image data C.sub.0,0, C.sub.0,1, . . . , C.sub.0,n. Similarly, the stripe 1 includes the image data C.sub.1,0, C.sub.1,1, . . . , C.sub.1,n. Further, the stripe S-1 includes the image data C.sub.S-1,0, C.sub.S-1,1, . . . , C.sub.S-1,n. Hereinafter, each of the image data C.sub.x,y (where x=0, . . . , n, y=0, . . . , n) is referred to as a "frame".
These frames are transferred in order from the lowest resolution frames to the highest. Herein, the order of being transferred in the same resolution's frames, is in the order of the stripe number. Namely, the order is as follows:
C.sub.0,0, C.sub.1,0, . . . , C.sub.S-1,0, C.sub.0,1, C.sub.1,1, . . . , C.sub.S-1,1, . . . , C.sub.0,n, C.sub.1,n, . . . , C.sub.S-1,n.
Conventionally, in such an image processing apparatus, when coded image data is inputted and stored in an image memory, the coded image data is stored in an address sequence of the image memory in accordance with the image data inputted sequence. When the stored image data is decoded in order to form an image in full resolution, non-consecutive addresses are supplied to the image memory, and the corresponding image data are read and decoded.
However, in the conventional technique, when the coded image data is decoded, since the coded image data needs to be read out from the image memory using the non-consecutive address accesses, a simple mechanism for increment/decrement of an address pointing to the image memory is not satisfactory, considering that a complicated address switching control is required. Accordingly, it takes considerable time to access the coded image data, making it impossible to perform high-speed decoding.
Furthermore, since the accessing process for the image memory use non-consecutive addresses, DMA (Direct Memory Access) transfer means cannot be used, making it difficult to perform high-speed decoding.